Hardware Engineer, Logical Design

The Normal Team builds foundational software and hardware that help move technology forward - supporting the semiconductor industry, critical AI infrastructure, and the broader systems that power our world. We work as one team across New York, San Francisco, Copenhagen, Seoul, and London.

Your Role in Our Mission:

You will define and implement architecture and microarchitecture for novel compute blocks at Normal Computing. This role requires both architectural thinking and hands-on RTL implementation-you'll work closely with architecture and research teams to translate high-level specifications into efficient hardware designs, then carry those designs through verification and physical implementation.

This is a role for engineers who are comfortable operating in ambiguity, where requirements and architectures evolve as we explore the design space. You should be equally capable of writing clean RTL, reasoning about architectures, and collaborating with physical design teams to ensure your designs can be built efficiently in silicon., * Define architecture and microarchitecture for novel compute blocks, collaborating closely with architecture and research teams

• Write high-quality RTL in SystemVerilog for core logic, datapaths, and control structures
• Work with DV team on digital verification for assigned designs, including testbench development, debugging, coverage, and signoff
• Work closely with physical design engineers to ensure RTL is implementable, performant, and aligned with layout constraints
• Contribute to functional or performance models to support early exploration, validation, and design tradeoff analysis
• Participate in design reviews, verification reviews, and cross-functional debug from concept through silicon
• Help shape internal RTL and verification methodologies in a fast-moving startup environment

Do you have experience in SystemVerilog?, Do you have a Master's degree?, * BS, MS, or PhD in Electrical / Electronic Engineering, Computer Engineering, Computer Science, or a related field

• 3+ years of experience in digital logic design, with meaningful ownership of blocks or subsystems
• Strong proficiency in SystemVerilog for RTL design and verification
• Experience designing compute cores, accelerators, or similarly complex logic
• Hands-on experience with digital verification, including testbench development, debugging, and coverage-driven validation
• Ability to work closely with physical design and verification teams to ensure correct, implementable designs
• Comfort operating in an R&D-focused, ambiguous environment where architecture, RTL, and verification evolve together

Bonus Points For:

• Experience with CDC/RDC analysis and mitigation in complex clocking or asynchronous designs
• Familiarity with modern verification methodologies and open source verification tools (UVM, Cocotb etc.)
• Experience with formal or semi-formal verification techniques (FPV, assertions, property checking)
• Prior work integrating third-party or internal IP into larger compute systems
• Experience building or improving verification flows, infrastructure, or automation
• Background in functional or performance modelling to support architecture exploration or validation